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ICCAD
1995
IEEE
77views Hardware» more  ICCAD 1995»
15 years 10 months ago
PARAS: system-level concurrent partitioning and scheduling
Partitioning for the ASIC designs is examined and the interaction between high-level synthesis and partitioning is studied and incorporated in the solution. Four algorithms (calle...
Wing Hang Wong, Rajiv Jain
DSD
2006
IEEE
113views Hardware» more  DSD 2006»
15 years 8 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...
ESANN
2008
15 years 8 months ago
Petri nets design based on neural networks
Petri net faulty models are useful for reliability analysis and fault diagnosis of discrete event systems. Such models are difficult to work out as long as they must be computed ac...
Edouard Leclercq, Souleiman Ould el Medhi, Dimitri...
FSMNLP
2008
Springer
15 years 8 months ago
Learning with Weighted Transducers
Weighted finite-state transducers have been used successfully in a variety of natural language processing applications, including speech recognition, speech synthesis, and machine ...
Corinna Cortes, Mehryar Mohri
FSTTCS
2008
Springer
15 years 7 months ago
Explicit Muller Games are PTIME
Regular games provide a very useful model for the synthesis of controllers in reactive systems. The complexity of these games depends on the representation of the winning condition...
Florian Horn