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» Algorithms for Interface Synthesis
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ISCAS
2005
IEEE
123views Hardware» more  ISCAS 2005»
16 years 6 days ago
Lower-bound estimation for multi-bitwidth scheduling
In high-level synthesis, accurate lower-bound estimation is helpful to explore the search space efficiently and to evaluate the quality of heuristic algorithms. For the lower-bound...
Junjuan Xu, Jason Cong, Xu Cheng
FPGA
2005
ACM
174views FPGA» more  FPGA 2005»
16 years 4 days ago
64-bit floating-point FPGA matrix multiplication
We introduce a 64-bit ANSI/IEEE Std 754-1985 floating point design of a hardware matrix multiplier optimized for FPGA implementations. A general block matrix multiplication algor...
Yong Dou, Stamatis Vassiliadis, Georgi Kuzmanov, G...
ISSS
1998
IEEE
73views Hardware» more  ISSS 1998»
15 years 11 months ago
Resource Constrained Modulo Scheduling with Global Resource Sharing
Commonly used scheduling algorithms in high-level synthesis are not capable of sharing resources across process boundaries. This results in the usage of at least one resource per ...
Christoph Jäschke, Rainer Laur
DAC
2004
ACM
15 years 10 months ago
Symmetry detection for incompletely specified functions
In this paper, we formulate symmetry detection for incompletely specified functions as an equation without using cofactor computation and equivalence checking. Based on this equat...
Kuo-Hua Wang, Jia-Hung Chen
EUC
2004
Springer
15 years 10 months ago
Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints
In archiectural synthesis, scheduling and resource allocation are important steps. During the early stage of the design, imprecise information is unavoidable. Under the imprecise ...
Chantana Chantrapornchai, Wanlop Surakumpolthorn, ...