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175
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DATE
2010
IEEE
15 years 12 months ago
2010
IEEE
—In a conventional SoC designs, on-chip memories occupy more than the 50% of the total die area. 3D technology enables the distribution of logic and memories on separate stacked ...
172
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CDC
2009
IEEE
15 years 11 months ago
2009
IEEE
— We study a clock calibration problem for an ultra-low power timer on a sensor node platform. When the sensor is put into sleep mode, this timer is the only thing left running, ...
171
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ISLPED
2009
ACM
15 years 11 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
167
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CVPR
1997
IEEE
15 years 11 months ago
1997
IEEE
— A number of active contour models have been proposed that unify the curve evolution framework with classical energy minimization techniques for segmentation, such as snakes. Th...
167
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ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
Abstract-- The increasing wire delay constraints in deep submicron VLSI designs have led to the emergence of scalable and modular Network-on-Chip (NoC) architectures. As the power ...