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DATE
2008
IEEE
116views Hardware» more  DATE 2008»
16 years 1 months ago
A Variation Aware High Level Synthesis Framework
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
Feng Wang 0004, Guangyu Sun, Yuan Xie
IEEEPACT
2007
IEEE
16 years 1 months ago
Automatic Correction of Loop Transformations
Loop nest optimization is a combinatorial problem. Due to the growing complexity of modern architectures, it involves two increasingly difficult tasks: (1) analyzing the profita...
Nicolas Vasilache, Albert Cohen, Louis-Noël P...
SIGMETRICS
2010
ACM
178views Hardware» more  SIGMETRICS 2010»
15 years 11 months ago
Optimality, fairness, and robustness in speed scaling designs
System design must strike a balance between energy and performance by carefully selecting the speed at which the system will run. In this work, we examine fundamental tradeoffs i...
Lachlan L. H. Andrew, Minghong Lin, Adam Wierman
DAC
2012
ACM
13 years 9 months ago
Towards fault-tolerant embedded systems with imperfect fault detection
Many state-of-the-art approaches on fault-tolerant system design make the simplifying assumption that all faults are detected within a certain time interval. However, based on a d...
Jia Huang, Kai Huang, Andreas Raabe, Christian Buc...
GECCO
2008
Springer
158views Optimization» more  GECCO 2008»
15 years 7 months ago
Objective reduction using a feature selection technique
This paper introduces two new algorithms to reduce the number of objectives in a multiobjective problem by identifying the most conflicting objectives. The proposed algorithms ar...
Antonio López Jaimes, Carlos A. Coello Coel...