In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
We study the problem on how to maximize the throughput for a periodic real-time system under the given peak temperature constraint. We assume that different tasks in our system ma...
We define a class of Guaranteed Rate (GR) scheduling algorithms. The GR class includes Virtual Clock, Packet-byPacket Generalized Processor Sharing and Self Clocked Fair Queuing....
With the growing number of marketplaces and trading partners in the e–commerce environment, software tools designed to act on behalf of human traders are increasingly used to au...
Yain-Whar Si, David Edmond, Arthur H. M. ter Hofst...
In this paper we study the problems of sorting and selection on the Distributed Memory Bus Computer (DMBC) recently introduced by Sahni. In particular we present: 1) An efficient a...