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CAV
2009
Springer
165views Hardware» more  CAV 2009»
16 years 7 months ago
Symbolic Counter Abstraction for Concurrent Software
Counter Abstraction for Concurrent Software G?erard Basler1 , Michele Mazzucchi1 , Thomas Wahl1,2 , Daniel Kroening1,2 1 Computer Systems Institute, ETH Zurich, Switzerland 2 Compu...
Daniel Kroening, Gérard Basler, Michele Maz...
200
Voted
HPCA
2009
IEEE
16 years 7 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
EUROSYS
2007
ACM
16 years 3 months ago
Dynamic and adaptive updates of non-quiescent subsystems in commodity operating system kernels
Continuously running systems require kernel software updates applied to them without downtime. Facilitating fast reboots, or delaying an update may not be a suitable solution in m...
Kristis Makris, Kyung Dong Ryu
ICCD
2008
IEEE
192views Hardware» more  ICCD 2008»
16 years 3 months ago
Energy-aware opcode design
— Embedded processors are required to achieve high performance while running on batteries. Thus, they must exploit all the possible means available to reduce energy consumption w...
Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte
168
Voted
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
16 years 3 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
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