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RE
2001
Springer
15 years 11 months ago
Events and Constraints: A Graphical Editor for Capturing Logic Requirements of Programs
A logic model checker can be an effective tool for debugging software applications. A stumbling block can be that model checking tools expect the user to supply a formal statement...
Margaret H. Smith, Gerard J. Holzmann, Kousha Etes...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
16 years 7 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
EUROMICRO
2007
IEEE
16 years 1 months ago
Partial Verification of Software Components: Heuristics for Environment Construction
Code model checking of software components suffers from the well-known problem of state explosion when applied to highly parallel components, despite the fact that a single compon...
Pavel Parizek, Frantisek Plasil
PRDC
2007
IEEE
16 years 1 months ago
An Automatic Real-Time Analysis of the Time to Reach Consensus
Consensus is one of the most fundamental problems in fault-tolerant distributed computing. This paper proposes a mechanical method for analyzing the condition that allows one to s...
Tatsuhiro Tsuchiya, André Schiper
FMCAD
2007
Springer
16 years 27 days ago
Induction in CEGAR for Detecting Counterexamples
— Induction has been studied in model checking for proving the validity of safety properties, i.e., showing the absence of counterexamples. To our knowledge, induction has not be...
Chao Wang, Aarti Gupta, Franjo Ivancic