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VTS
2003
IEEE
95views Hardware» more  VTS 2003»
15 years 12 months ago
Built-In Reseeding for Serial Bist
Reseeding is used to improve fault coverage in pseudo-random testing. Most of the work done on reseeding is based on storing the seeds in an external tester. Besides its high cost...
Ahmad A. Al-Yamani, Edward J. McCluskey
DAC
2003
ACM
15 years 12 months ago
Efficient compression and application of deterministic patterns in a logic BIST architecture
We present a novel method to efficiently generate, compress and apply test patterns in a logic BIST architecture. Patterns are generated by a modified automatic test pattern gener...
Peter Wohl, John A. Waicukauski, Sanjay Patel, Min...
DATE
2000
IEEE
130views Hardware» more  DATE 2000»
15 years 11 months ago
Optimal Hardware Pattern Generation for Functional BIST
∗∗ Functional BIST is a promising solution for self-testing complex digital systems at reduced costs in terms of area and performance degradation. The present paper addresses t...
Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, H...
IV
1999
IEEE
151views Visualization» more  IV 1999»
15 years 11 months ago
Occlusion Culling Using Minimum Occluder Set and Opacity Map
The aim of occlusion culling is to cull away a significant amount of invisible primitives at different viewpoints. We present two algorithms to improve occlusion culling for a hig...
Poon Chun Ho, Wenping Wang
VTS
1995
IEEE
100views Hardware» more  VTS 1995»
15 years 10 months ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey