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VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
16 years 15 days ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
AMOST
2007
ACM
15 years 10 months ago
Using LTL rewriting to improve the performance of model-checker based test-case generation
Model-checkers have recently been suggested for automated software test-case generation. Several works have presented methods that create efficient test-suites using model-checker...
Gordon Fraser, Franz Wotawa
DAC
2007
ACM
16 years 7 months ago
Scan Test Planning for Power Reduction
Many STUMPS architectures found in current chip designs allow disabling of individual scan chains for debug and diagnosis. In a recent paper it has been shown that this feature can...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
CEC
2009
IEEE
16 years 1 months ago
An evaluation of Differential Evolution in software test data generation
— One of the main tasks software testing involves is the generation of the test inputs to be used during the test. Due to its expensive cost, the automation of this task has beco...
Ricardo Landa Becerra, Ramón Sagarna, Xin Y...
ATVA
2009
Springer
117views Hardware» more  ATVA 2009»
16 years 1 months ago
UnitCheck: Unit Testing and Model Checking Combined
Code model checking is a rapidly advancing research topic. However, apart from very constrained scenarios (e.g., verification of device drivers by Slam), the code model checking t...
Michal Kebrt, Ondrej Sery