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ATS
2005
IEEE
118views Hardware» more  ATS 2005»
16 years 3 days ago
Partial Gating Optimization for Power Reduction During Test Application
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ra...
FASE
2004
Springer
15 years 12 months ago
Systematic Testing of Software Architectures in the C2 Style
The topic of software architecture (SA) based testing has recently raised some interest. Recent work on the topic has used the SA as a reference model for code conformance testing,...
Henry Muccini, Marcio S. Dias, Debra J. Richardson
ET
2010
113views more  ET 2010»
15 years 3 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
ICST
2011
IEEE
14 years 10 months ago
Applying aggressive propagation-based strategies for testing changes
—Test-suite augmentation for evolving software— the process of augmenting a test suite to adequately test software changes—is necessary for any program that undergoes modifi...
Raúl A. Santelices, Mary Jean Harrold
SIGUCCS
2004
ACM
15 years 12 months ago
A platform independent tool for evaluating performance of computing equipment for a computer laboratory
Designing computing equipment for a computer laboratory is not easy. In a class in a computer laboratory, it is not unusual that all students do the same thing simultaneously. Tre...
Takashi Yamanoue