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SBCCI
2005
ACM
185views VLSI» more  SBCCI 2005»
16 years 1 days ago
Automatic generation of test sets for SBST of microprocessor IP cores
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...
Ernesto Sánchez, Matteo Sonza Reorda, Giova...
ISQED
2002
IEEE
203views Hardware» more  ISQED 2002»
15 years 11 months ago
Automatic Test Program Generation from RT-Level Microprocessor Descriptions
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two p...
Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda...
ICSE
1999
IEEE-ACM
15 years 10 months ago
Residual Test Coverage Monitoring
Structural coverage criteria are often used as an indicator of the thoroughness of testing, but complete satisfaction of a criterion is seldom achieved. When a software product is...
Christina Pavlopoulou, Michal Young
DELTA
2004
IEEE
15 years 10 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
ITC
1991
IEEE
86views Hardware» more  ITC 1991»
15 years 10 months ago
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Two approaches have been used to balance the cost of generating e ective tests for ICs and the need to increase the ICs' quality level. The rst approach favorsusing high-leve...
F. Joel Ferguson, Tracy Larrabee