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ICCD
2005
IEEE
116views Hardware» more  ICCD 2005»
16 years 3 months ago
Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis
Consideration of pairs of transition in probabilistic simulation allows power estimation for digital circuits in which inertial delays can filter glitches [5]. However, the merit ...
Fei Hu, Vishwani D. Agrawal
ICCD
2003
IEEE
147views Hardware» more  ICCD 2003»
16 years 3 months ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-...
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
16 years 1 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
ISAAC
2009
Springer
109views Algorithms» more  ISAAC 2009»
16 years 1 months ago
A Linear Vertex Kernel for Maximum Internal Spanning Tree
We present an algorithm that for any graph G and integer k ≥ 0 in time polynomial in the size of G either nds a spanning tree with at least k internal vertices, or outputs a ne...
Fedor V. Fomin, Serge Gaspers, Saket Saurabh, St&e...
IWPEC
2009
Springer
16 years 1 months ago
Even Faster Algorithm for Set Splitting!
In the p-Set Splitting problem we are given a universe U, a family F of subsets of U and a positive integer k and the objective is to find a partition of U into W and B such that...
Daniel Lokshtanov, Saket Saurabh