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216
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ICS
1999
Tsinghua U.
15 years 11 months ago
1999
Tsinghua U.
On modern computers, the performance of programs is often limited by memory latency rather than by processor cycle time. To reduce the impact of memory latency, the restructuring ...
155
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FOCS
1998
IEEE
15 years 11 months ago
1998
IEEE
In the Finite Capacity Dial-a-Ride problem the input is a metric space, a set of objects {di}, each specifying a source si and a destination ti, and an integer k--the capacity of t...
214
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LCTRTS
1999
Springer
15 years 11 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
179
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IPPS
1998
IEEE
15 years 11 months ago
1998
IEEE
Instruction scheduling methods based on the construction of state diagrams (or automata) have been used for architectures involving deeply pipelined function units. However, the s...
203
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SCCC
1998
IEEE
15 years 11 months ago
1998
IEEE
We present a scalable algorithm for the parallel computation of inverted files for large text collections. The algorithm takes into account an environment of a high bandwidth netw...