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MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
16 years 22 days ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 10 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
GIS
2006
ACM
16 years 7 months ago
Object localization based on directional information case of 2D vector data
If you were told that some object A was perfectly (or somewhat, or not at all) in some direction (e.g., west, above-right) of some reference object B, where in space would you loo...
Stelian Coros, JingBo Ni, Pascal Matsakis
NIPS
2007
15 years 7 months ago
Modeling Natural Sounds with Modulation Cascade Processes
Natural sounds are structured on many time-scales. A typical segment of speech, for example, contains features that span four orders of magnitude: Sentences (∼1 s); phonemes (âˆ...
Richard Turner, Maneesh Sahani
ICASSP
2008
IEEE
16 years 27 days ago
A factor graph approach to joint iterative data detection and channel estimation in pilot-assisted IDMA transmissions
We consider a pilot-assisted interleave-division multiple access (IDMA) system transmitting over block-fading channels. We describe this system in terms of a factor graph and use ...
Clemens Novak, Gerald Matz, Franz Hlawatsch