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ISQED
2002
IEEE
168views Hardware» more  ISQED 2002»
15 years 11 months ago
ALBORZ: Address Level Bus Power Optimization
In this paper we introduce a new low power address bus encoding technique, and the resulting code, named ALBORZ. The ALBORZ code is constructed based on transition signaling the l...
Yazdan Aghaghiri, Farzan Fallah, Massoud Pedram
LICS
1999
IEEE
15 years 10 months ago
The Higher-Order Recursive Path Ordering
This paper extends the termination proof techniques based on reduction orderings to a higher-order setting, by adapting the recursive path ordering definition to terms of a typed ...
Jean-Pierre Jouannaud, Albert Rubio
MICRO
2009
IEEE
159views Hardware» more  MICRO 2009»
16 years 1 months ago
Adaptive line placement with the set balancing cache
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
Dyer Rolán, Basilio B. Fraguela, Ramon Doal...
DATE
2008
IEEE
134views Hardware» more  DATE 2008»
16 years 27 days ago
Adaptive Filesystem Compression for Embedded Systems
Abstract—Embedded system secondary storage size is often constrained, yet storage demands are growing as a result of increasing application complexity and storage of personal dat...
Lan S. Bai, Haris Lekatsas, Robert P. Dick
ICCD
2008
IEEE
148views Hardware» more  ICCD 2008»
16 years 26 days ago
Adaptive SRAM memory for low power and high yield
— SRAMs typically represent half of the area and more than half of the transistors on a chip today. Variability increases as feature size decreases, and the impact of variability...
Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jaco...