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195
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EURODAC
1990
IEEE
15 years 11 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
182
Voted
ICFEM
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. CSP is a well-established formalism for modelling and verification of concurrent reactive systems based on refinement. Consolidated denotational models and an effective t...
167
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ASPDAC
2006
ACM
15 years 10 months ago
2006
ACM
- This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) Silicon-On-Insulator (SOI) CMOS technology. We me...
187
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
188
Voted
DFT
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper presents a novel delay fault testing technique, which can be used as an alternative to the enhanced scan based delay fault testing, with significantly less design overh...