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MSE
2003
IEEE
101views Hardware» more  MSE 2003»
16 years 4 days ago
Internet-based Tool for System-On-Chip Project Testing and Grading
A tool has been developed to automate the testing and grading of design projects implemented in reprogrammable hardware. The server allows multiple students to test circuits in FP...
Christopher K. Zuver, Christopher E. Neely, John W...
169
Voted
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
15 years 11 months ago
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
Michael Pronath, Helmut E. Graeb, Kurt Antreich
APN
2001
Springer
15 years 11 months ago
Optimising Enabling Tests and Unfoldings of Algebraic System Nets
Reachability analysis and simulation tools for high-level nets spend a significant amount of the computing time in performing enabling tests, determining the assignments under whi...
Marko Mäkelä
ITC
2000
IEEE
80views Hardware» more  ITC 2000»
15 years 11 months ago
A stand-alone integrated test core for time and frequency domain measurements
An area efficient and robust integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstructi...
Mohamed Hafed, Nazmy Abaskharoun, Gordon W. Robert...
DATE
1998
IEEE
88views Hardware» more  DATE 1998»
15 years 11 months ago
Functional Scan Chain Testing
Functional scan chains are scan chains that have scan paths through a circuit's functional logic and flip-flops. Establishing functional scan paths by test point insertion (T...
Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-...