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DFT
2000
IEEE
105views VLSI» more  DFT 2000»
15 years 11 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
153
Voted
DSN
2000
IEEE
15 years 11 months ago
Testing for Software Vulnerability Using Environment Perturbation
We describe an methodology for testing a software system for possible security flaws. Based on the observation that most security flaws are caused by the program’s inappropria...
Wenliang Du, Aditya P. Mathur
VTS
2000
IEEE
94views Hardware» more  VTS 2000»
15 years 11 months ago
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
1 This paper addresses the problem of testing path delay faults in a microprocessor using instructions. It is observed that a structurally testable path (i.e., a path testable thro...
Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
SIGSOFT
2000
ACM
15 years 11 months ago
Automated systematic testing for constraint-based interactive services
Constraint-based languages can express in a concise way the complex logic of a new generation of interactive services for applications such as banking or stock trading, that must ...
Patrice Godefroid, Lalita Jategaonkar Jagadeesan, ...
DFT
1999
IEEE
75views VLSI» more  DFT 1999»
15 years 11 months ago
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths
Fault identification capabilities are becoming increasingly important in modern designs, not only in support of design debugging methodologies, but also for the purpose of process...
Yiorgos Makris, Alex Orailoglu