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DATE
2007
IEEE
93views Hardware» more  DATE 2007»
16 years 1 months ago
Testing in the year 2020
Testing today of a several hundred million transistor System-on-Chip with analog, RF blocks, many processor cores and tens of memories is a huge task. What will test technology be...
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
DFT
2007
IEEE
123views VLSI» more  DFT 2007»
16 years 1 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
HASE
2007
IEEE
16 years 1 months ago
Advances in Quantum Computing Fault Tolerance and Testing
We study recent developments in quantum computing (QC) testing and fault tolerance (FT) techniques and discuss several attempts to formalize quantum logic fault models. We illustr...
David Y. Feinstein, V. S. S. Nair, Mitchell A. Tho...
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
16 years 25 days ago
Extraction of defect density and size distributions from wafer sort test results
Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used t...
Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jas...
ISSRE
2006
IEEE
16 years 24 days ago
Testing During Refactoring: Adding Aspects to Legacy Systems
Moving program code that implements cross-cutting concerns into aspects can improve the maintainability of legacy systems. This kind of refactoring, called aspectualization, can a...
Michael Mortensen, Sudipto Ghosh, James M. Bieman