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129
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ICCAD
2008
IEEE
105views Hardware» more  ICCAD 2008»
16 years 3 months ago
Temperature-aware test scheduling for multiprocessor systems-on-chip
—Increasing power densities due to process scaling, combined with high switching activity and poor cooling environments during testing, have the potential to result in high integ...
David R. Bild, Sanchit Misra, Thidapat Chantem, Pr...
DATE
2009
IEEE
78views Hardware» more  DATE 2009»
16 years 1 months ago
QC-Fill: An X-Fill method for quick-and-cool scan test
— In this paper, we present an X-Fill (QC-Fill) method for not only slashing the test time but also reducing the test power (including both capture power and shifting power). QC-...
Chao-Wen Tzeng, Shi-Yu Huang
ICASSP
2008
IEEE
16 years 1 months ago
Composite hypothesis testing by optimally distinguishable distributions
Relying on optimally distinguishable distributions (ODD), it was defined very recently a new framework for the composite hypothesis testing. We resort to the linear model to inve...
Seyed Alireza Razavi, Ciprian Doru Giurcaneanu
169
Voted
VLSID
2008
IEEE
122views VLSI» more  VLSID 2008»
16 years 1 months ago
Testing Flash Memories for Tunnel Oxide Defects
— Testing non volatile memories for tunnel oxide defects is one of the most important aspects to guarantee cell reliability. Defective tunnel oxide layer in core memory cells can...
Mohammad Gh. Mohammad, Kewal K. Saluja
DATE
2007
IEEE
109views Hardware» more  DATE 2007»
16 years 1 months ago
Toward a scalable test methodology for 2D-mesh Network-on-Chips
1 This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the ...
Kim Petersén, Johnny Öberg