A tunneling-open failure mode is proposed and carefully studied. A circuit with a tunneling open could pass at-speed Boolean tests but fail VLV testing or IDDQ testing. Theoretica...
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer