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ITC
2000
IEEE
76views Hardware» more  ITC 2000»
15 years 11 months ago
Testing for tunneling opens
A tunneling-open failure mode is proposed and carefully studied. A circuit with a tunneling open could pass at-speed Boolean tests but fail VLV testing or IDDQ testing. Theoretica...
Chien-Mo James Li, Edward J. McCluskey
VTS
2000
IEEE
97views Hardware» more  VTS 2000»
15 years 11 months ago
A Low-Speed BIST Framework for High-Performance Circuit Testing
Testing of high performance integrated circuits is becoming increasingly a challenging task owing to high clock frequencies. Often testers are not able to test such devices due to...
Hans G. Kerkhoff, Mansour Shashaani, Manoj Sachdev
VTS
2000
IEEE
76views Hardware» more  VTS 2000»
15 years 11 months ago
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
Sule Ozev, Alex Orailoglu
DATE
1999
IEEE
85views Hardware» more  DATE 1999»
15 years 11 months ago
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
Jongchul Shin, Hyunjin Kim, Sungho Kang
VTS
1999
IEEE
71views Hardware» more  VTS 1999»
15 years 11 months ago
Test Generation for Ground Bounce in Internal Logic Circuitry
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer