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DATE
1999
IEEE
76views Hardware» more  DATE 1999»
15 years 11 months ago
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's
The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM...
Michel Renovell, Jean Michel Portal, Joan Figueras...
ISORC
1998
IEEE
15 years 11 months ago
Automating Regression Testing for Real-Time Software in a Distributed Environment
Many real-time systems evolve over time due to new requirements and technology improvements. Each revision requires regression testing to ensure that existing functionality is not...
Feng Zhu, Sanjai Rayadurgam, Wei-Tek Tsai
APSEC
1996
IEEE
15 years 10 months ago
A Prototype of a Concurrent Behavior Monitoring Tool for Testing of Concurrent Programs
Testing of concurrent programs is much more difficult than that of sequential programs. A concurrent program behaves nondeterministically, that is, the program may produce differe...
Eisuke Itoh, Zengo Furukawa, Kazuo Ushijima
DATE
2009
IEEE
88views Hardware» more  DATE 2009»
15 years 10 months ago
A generic framework for scan capture power reduction in fixed-length symbol-based test compression environment
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
Xiao Liu, Qiang Xu
DDECS
2009
IEEE
149views Hardware» more  DDECS 2009»
15 years 10 months ago
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing
Although the Neighborhood Pattern Sensitive Fault (NPSF) model is recognized as a high quality fault model for memory arrays, the excessive test application time cost associated wi...
Yiorgos Sfikas, Yiorgos Tsiatouhas