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EVOW
1999
Springer
15 years 11 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
150
Voted
ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
15 years 11 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
15 years 11 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
KBSE
1998
IEEE
15 years 11 months ago
An Automated Framework for Structural Test-Data Generation
Structural testing criteria are mandated in many software development standards and guidelines. The process of generating test-data to achieve 100 coverage of a given structural c...
Nigel Tracey, John A. Clark, Keith Mander, John A....
134
Voted
ATS
1997
IEEE
88views Hardware» more  ATS 1997»
15 years 11 months ago
On the Adders with Minimum Tests
This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at fault models. In the first part, we prese...
Seiji Kajihara, Tsutomu Sasao