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VTS
2002
IEEE
108views Hardware» more  VTS 2002»
15 years 11 months ago
On Using Efficient Test Sequences for BIST
High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
René David, Patrick Girard, Christian Landr...
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
15 years 11 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
ITC
1999
IEEE
178views Hardware» more  ITC 1999»
15 years 11 months ago
Embedded X86 testing methodology
The embedded core testing methodology at Advanced Micro Devices Inc. involves adopting a disciplined system for developing new products with a focus on time to market and engineer...
Luis Basto, Asif Khan, Pete Hodakievic
ITC
1999
IEEE
67views Hardware» more  ITC 1999»
15 years 11 months ago
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper prese...
Phil Nigh, David P. Vallett, Atul Patel, Jason Wri...
ITC
1999
IEEE
103views Hardware» more  ITC 1999»
15 years 11 months ago
Resistive bridge fault modeling, simulation and test generation
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
Vijay R. Sar-Dessai, D. M. H. Walker