High defect coverage requires good coverage of different fault types. In this paper, we present a comprehensive test vector generation technique for BIST, called Random Single Inp...
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
The embedded core testing methodology at Advanced Micro Devices Inc. involves adopting a disciplined system for developing new products with a focus on time to market and engineer...
SEMATECH has sponsored a "Test Method Evaluation" study to understand the trade-offs among the most common test methodologies used in the industry[1,2]. This paper prese...
Phil Nigh, David P. Vallett, Atul Patel, Jason Wri...
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...