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ATS
2003
IEEE
87views Hardware» more  ATS 2003»
15 years 12 months ago
March SL: A Test For All Static Linked Memory Faults
The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all ...
Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mik...
COMPSAC
2003
IEEE
15 years 12 months ago
Tolerance of Control-Flow Testing Criteria
Effectiveness of testing criteria is the ability to detect failures in a software program. We consider not only effectiveness of some testing criterion in itself but a variance of...
Sergiy A. Vilkomir, Kalpesh Kapoor, Jonathan P. Bo...
DATE
2003
IEEE
105views Hardware» more  DATE 2003»
15 years 12 months ago
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation
: Stresses are considered an integral part of any modern industrial DRAM test. This paper describes a novel method to optimize stresses for memory testing, using defect injection a...
Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev...
ITC
2003
IEEE
115views Hardware» more  ITC 2003»
15 years 12 months ago
Towards Structural Testing of Superconductor Electronics
Many of the semiconductor technologies are already facing limitations while new-generation data and telecommunication systems are implemented. Although in its infancy, superconduc...
Arun A. Joseph, Hans G. Kerkhoff
DAC
2003
ACM
15 years 11 months ago
Test generation for designs with multiple clocks
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
Xijiang Lin, Rob Thompson