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DATE
2006
IEEE
98views Hardware» more  DATE 2006»
16 years 19 days ago
Test generation for combinational quantum cellular automata (QCA) circuits
— In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted significant recent at...
Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
GLVLSI
2006
IEEE
95views VLSI» more  GLVLSI 2006»
16 years 19 days ago
Test generation using SAT-based bounded model checking for validation of pipelined processors
Functional verification is one of the major bottlenecks in microprocessor design. Simulation-based techniques are the most widely used form of processor verification. Efficient ...
Heon-Mo Koo, Prabhat Mishra
ATS
2005
IEEE
121views Hardware» more  ATS 2005»
16 years 6 days ago
Compressing Functional Tests for Microprocessors
In the past, test data volume reduction techniques have concentrated heavily on scan test data content. However, functional vectors continue to be utilized because they target uni...
Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas ...
CEC
2005
IEEE
16 years 6 days ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
16 years 5 days ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...