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COMPSAC
2002
IEEE
15 years 11 months ago
Temporal Modeling of Software Test Coverage
This paper presents a temporal model for the coverage achieved by software testing. The proposed model, which is applicable at any level of the testing hierarchy, can determine th...
Sahra Sedigh-Ali, Arif Ghafoor, Raymond A. Paul
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
15 years 11 months ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
ISSRE
2002
IEEE
15 years 11 months ago
Test Reuse in the Spreadsheet Paradigm
Spreadsheet languages are widely used by a variety of end users to perform many important tasks. Despite their perceived simplicity, spreadsheets often contain faults. Furthermore...
Marc Fisher II, Dalai Jin, Gregg Rothermel, Margar...
DATE
1998
IEEE
106views Hardware» more  DATE 1998»
15 years 10 months ago
March Tests for Word-Oriented Memories
Most memory test algorithms are optimized tests for a particular memory technology and a particular set of fault models, under the assumption that the memory is bit-oriented; i.e....
A. J. van de Goor, Issam B. S. Tlili
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 10 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...