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DATE
2010
IEEE
149views Hardware» more  DATE 2010»
15 years 11 months ago
Efficient decision ordering techniques for SAT-based test generation
Model checking techniques are promising for automated generation of directed tests. However, due to the prohibitively large time and resource requirements, conventional model chec...
Mingsong Chen, Xiaoke Qin, Prabhat Mishra
ICCAD
1997
IEEE
147views Hardware» more  ICCAD 1997»
15 years 10 months ago
Built-in test generation for synchronous sequential circuits
We consider the problem of built-in test generation for synchronous sequential circuits. The proposed scheme leaves the circuit flip-flops unmodified, and thus allows at-speed ...
Irith Pomeranz, Sudhakar M. Reddy
VTS
1997
IEEE
96views Hardware» more  VTS 1997»
15 years 10 months ago
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
ICCAD
1996
IEEE
94views Hardware» more  ICCAD 1996»
15 years 10 months ago
Metrology for analog module testing using analog testability bus
In this paper, we propose a method to generate high quality test waveform on chip to avoid the parasitic eects in an analog testability bus test environment. For the test response...
Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou, Yuan-Tz...
ICSE
1997
IEEE-ACM
15 years 10 months ago
Choosing a Testing Method to Deliver Reliability
Testing methods are compared in a model where program failures are detected and the software changed to eliminate them. The question considered is whether it is better to use test...
Phyllis G. Frankl, Richard G. Hamlet, Bev Littlewo...