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DATE
2006
IEEE
85views Hardware» more  DATE 2006»
16 years 17 days ago
Test set enrichment using a probabilistic fault model and the theory of output deviations
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
Zhanglei Wang, Krishnendu Chakrabarty, Michael G&o...
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
16 years 17 days ago
Power-constrained test scheduling for multi-clock domain SoCs
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
ETS
2006
IEEE
93views Hardware» more  ETS 2006»
16 years 17 days ago
Retention-Aware Test Scheduling for BISTed Embedded SRAMs
In this paper we address the test scheduling problem for Builtin Self-tested (BISTed) embedded SRAMs (e-SRAMs) when Data Retention Faults (DRFs) are considered. The proposed test ...
Qiang Xu, Baosheng Wang, F. Y. Young
ISSRE
2006
IEEE
16 years 16 days ago
Studying the Characteristics of a "Good" GUI Test Suite
The widespread deployment of graphical-user interfaces (GUIs) has increased the overall complexity of testing. A GUI test designer needs to perform the daunting task of adequately...
Qing Xie, Atif M. Memon
ISSTA
2006
ACM
16 years 14 days ago
Subdomain testing of units and systems with state
This paper extends basic software-testing theory to software components and adds explicit state to the theory. The resulting theory e enough to abstractly model the construction o...
Dick Hamlet