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149
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GD
2004
Springer
15 years 12 months ago
2004
Springer
The upward planarity testing problem consists of testing if a digraph admits a drawing Γ such that all edges in Γ are monotonically increasing in the vertical direction and no e...
142
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MTDT
2003
IEEE
15 years 11 months ago
2003
IEEE
: Linked faults are very important for memory testing because they reduce the fault coverage of the tests. Their analysis has proven to be a source for new memory tests, characteri...
136
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper in...
164
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VTS
1997
IEEE
15 years 10 months ago
1997
IEEE
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
176
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DEXAW
2008
IEEE
15 years 8 months ago
2008
IEEE
Validation is an essential part of software development, and testing is a practical and widely used approach. The emerging methodology is model-based testing, in which test cases ...