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DATE
2002
IEEE
80views Hardware» more  DATE 2002»
15 years 11 months ago
Test Planning and Design Space Exploration in a Core-Based Environment
This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the considerati...
Érika F. Cota, Luigi Carro, Marcelo Lubasze...
ICTAI
2002
IEEE
15 years 11 months ago
A Genetic Testing Framework for Digital Integrated Circuits
In order to reduce the time-to-market and simplify gatelevel test generation for digital integrated circuits, GAbased functional test generation techniques are proposed for behavi...
Xiaoming Yu, Alessandro Fin, Franco Fummi, Elizabe...
DATE
1999
IEEE
91views Hardware» more  DATE 1999»
15 years 10 months ago
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks
In this paper we show that the already known method of using multiplexers for making the inputs and outputs of the embedded blocks accessible by the primary ports of the Integrate...
Dimitris Nikolos, Haridimos T. Vergos, Th. Haniota...
ITC
1999
IEEE
59views Hardware» more  ITC 1999»
15 years 10 months ago
Static component interconnection test technology in practice
Static Component Interconnection Test Technology (SCITT) is a new XNOR circuit based technology that is used for board-level interconnection test. SCITT provides an easy test meth...
Frans De Jong, Rob Raaijmakers
ATS
1996
IEEE
117views Hardware» more  ATS 1996»
15 years 10 months ago
Hierarchical Test Generation with Built-In Fault Diagnosis
A hierarchical test generation method is presented that uses the inherent hierarchical structure of the circuit under test and takes fault diagnosability into account right from t...
Dirk Stroobandt, Jan Van Campenhout