Sciweavers

3865 search results - page 572 / 773
» Active memory operations
Sort
View
ISCA
2005
IEEE
118views Hardware» more  ISCA 2005»
16 years 5 days ago
Continuous Optimization
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steve...
ISCAS
2005
IEEE
152views Hardware» more  ISCAS 2005»
16 years 5 days ago
Dictionary-based program compression on transport triggered architectures
— Program code size has become a critical design constraint of embedded systems. Large program codes require large memories, which increase the size and cost of the chip. Poor co...
Jari Heikkinen, Andrea G. M. Cilio, Jarmo Takala, ...
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
16 years 5 days ago
HIBI-based multiprocessor SoC on FPGA
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
MMM
2005
Springer
148views Multimedia» more  MMM 2005»
16 years 5 days ago
Paving the Last Mile for Multi-Channel Multimedia Presentation Generation
Users of multimedia applications today are equipped with a variety of different (mobile) devices that each come with different operating systems, memory and CPU capabilities, netw...
Ansgar Scherp, Susanne Boll
VISUALIZATION
2005
IEEE
16 years 5 days ago
VolQD: Direct Volume Rendering of Multi-million Atom Quantum Dot Simulations
In this work we present a hardware-accelerated direct volume rendering system for visualizing multivariate wave functions in semiconducting quantum dot (QD) simulations. The simul...
Wei Qiao, David S. Ebert, Alireza Entezari, Marek ...