3865 search results - page 458 / 773 » Active memory operations |
209
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SBRN
2000
IEEE
15 years 11 months ago
2000
IEEE
This paper proposes a simple methodology to construct an iterative neural network which mimics a given chaotic time series. The methodology uses the Gamma test to identify a suita...
186
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DAC
2000
ACM
15 years 11 months ago
2000
ACM
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
164
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SIGGRAPH
1999
ACM
15 years 11 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
184
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IPCCC
1999
IEEE
15 years 11 months ago
1999
IEEE
Many computer hardware and software architectures buffer data in memory to improve system performance. Volatile disk or file caches are sometimes used to delay the propagation of ...
175
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IPPS
1999
IEEE
15 years 11 months ago
1999
IEEE
An e cient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs...