Sciweavers

3865 search results - page 444 / 773
» Active memory operations
Sort
View
SAMOS
2004
Springer
16 years 3 days ago
with Wide Functional Units
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
Miquel Pericàs, Eduard Ayguadé, Javi...
BTW
2003
Springer
110views Database» more  BTW 2003»
16 years 9 hour ago
The IOP Approach to Enterprise Frameworks
Abstract: This paper introduces the Internet Operating Platform (IOP), an enterprise framework for large scale software development. In addition to obeying to important standards (...
Udo Nink, Stefan Schäfer
ICCAD
2002
IEEE
112views Hardware» more  ICCAD 2002»
15 years 11 months ago
ATPG-based logic synthesis: an overview
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
IPPS
2002
IEEE
15 years 11 months ago
Implementing the NAS Benchmark MG in SAC
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
Clemens Grelck
PDP
2002
IEEE
15 years 11 months ago
A Hardware-Accelerated Novel IR System
AURA (Advanced Uncertain Reasoning Architecture) is a generic family of techniques and implementations intended for high-speed approximate search and match operations on large uns...
Michael Weeks, Victoria J. Hodge, Jim Austin