197 search results - page 10 / 40 » Abstraction Techniques for Validation Coverage Analysis and ... |
153
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KBSE
2007
IEEE
16 years 7 days ago
2007
IEEE
We present CESE, a tool that combines exhaustive enumeration of test inputs from a structured domain with symbolic execution driven test generation. We target programs whose valid...
179
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DATE
2009
IEEE
16 years 21 days ago
2009
IEEE
—Verification is a major issue in circuit and system design. Formal methods like bounded model checking (BMC) can guarantee a high quality of the verification. There are severa...
157
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KBSE
1998
IEEE
15 years 10 months ago
1998
IEEE
Structural testing criteria are mandated in many software development standards and guidelines. The process of generating test-data to achieve 100 coverage of a given structural c...
156
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DATE
1997
IEEE
15 years 9 months ago
1997
IEEE
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
211
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ICST
2010
IEEE
15 years 4 months ago
2010
IEEE
Abstract—Software Product Lines (SPL) are difficult to validate due to combinatorics induced by variability across their features. This leads to combinatorial explosion of the n...