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» Abstraction, Levels of Detail, and Hierarchies in Map Series
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LCTRTS
1998
Springer
15 years 10 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
ISCAPDCS
2004
15 years 7 months ago
FG: A Framework Generator for Hiding Latency in Parallel Programs Running on Clusters
FG is a programming environment for asynchronous programs that run on clusters and fit into a pipeline framework. It enables the programmer to write a series of synchronous functi...
Thomas H. Cormen, Elena Riccio Davidson
IEEECIT
2005
IEEE
15 years 11 months ago
iCDMdt: Focused the Model Mapping and Performance Optimization in Embedded System Design
This paper proposes a method of model-driven HW/SW co-design in embedded system design and discusses the key technology of model mapping, automatic generating codes and performanc...
Jing Luan, Xuan Cheng, Junzhong Gu
COMPSAC
2009
IEEE
15 years 10 months ago
Transaction Level Control for Application Execution on the SegBus Platform
Abstract—We define here a simple, low level control procedure definition, to support application implementation on a particular multiprocessor platform, namely the SegBus segme...
Tiberiu Seceleanu, Ivica Crnkovic, Cristina Cersch...
ICDE
2010
IEEE
174views Database» more  ICDE 2010»
15 years 4 months ago
Semantic flooding: Search over semantic links
Abstract-- Classification hierarchies are trees where links codify the fact that a node lower in the hierarchy contains documents whose contents are more specific than those one le...
Fausto Giunchiglia, Uladzimir Kharkevich, Alethia ...