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187
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TACAS
2005
Springer
16 years 7 days ago
2005
Springer
Abstract. Symmetry reduction is a technique to combat the state explosion problem in temporal logic model checking. Its use with symbolic representation has suffered from the proh...
167
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WIA
2004
Springer
16 years 2 days ago
2004
Springer
d abstract) Gaoyan Xie, Cheng Li, and Zhe Dang School of Electrical Engineering and Computer Science Washington State University Pullman, WA 99164, USA Abstract. In this paper, ...
168
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VLSID
1999
IEEE
15 years 11 months ago
1999
IEEE
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
165
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...
167
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FMOODS
2007
15 years 8 months ago
2007
We present the first tool that offers dynamic verification of extended traints on UML models. It translates a UML model into an Abstract State (ASM) which is transformed by an AS...