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PARA
1998
Springer
15 years 10 months ago
Technologies for Teracomputing: A European Option
Abstract. Ahardware and software environment with performance above 1 Tera ops (teracomputing) is presently required to face the leading computational challenges not only in fundam...
Agostino Mathis
CODES
2004
IEEE
15 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
WM
2003
15 years 7 months ago
Experience Management within Project Management Processes
: The business process revolution has had two impacts on project management: the recognition of a process perspective (such as the 39 appearing in the PMBOK), and the acknowledgeme...
Maya Kaner, Reuven Karni
ISVLSI
2002
IEEE
109views VLSI» more  ISVLSI 2002»
15 years 11 months ago
A Network on Chip Architecture and Design Methodology
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnn...
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 12 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane