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VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
16 years 7 months ago
Interframe Bus Encoding Technique for Low Power Video Compression
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
VLSID
2006
IEEE
170views VLSI» more  VLSID 2006»
16 years 7 months ago
On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder
This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have ...
Koushik Maharatna, Alfonso Troya, Milos Krstic, Ec...
VLSID
2003
IEEE
253views VLSI» more  VLSID 2003»
16 years 7 months ago
High Level Synthesis from Sim-nML Processor Models
The design of modern complex embedded systems require a high level of abstraction of the design. The SimnML[1] is a specification language to model processors for such designs. Se...
Souvik Basu, Rajat Moona
VLSID
2002
IEEE
130views VLSI» more  VLSID 2002»
16 years 7 months ago
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks
In preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT) of the tasks can be obtained if the layout of the tasks in memory is included in the esti...
Anupam Datta, Sidharth Choudhury, Anupam Basu
VLSID
2002
IEEE
152views VLSI» more  VLSID 2002»
16 years 7 months ago
Verification of an Industrial CC-NUMA Server
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...
Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima