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HPCA
2001
IEEE
16 years 7 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
ISCAS
2007
IEEE
133views Hardware» more  ISCAS 2007»
16 years 1 months ago
Design of a Massively Parallel Vision Processor based on Multi-SIMD Architecture
— Increasing demands for robust image recognition systems require vision processors not only with enormous computational capacities but also with sufficient flexibility to hand...
Kota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro...
DIGRA
2005
Springer
16 years 7 days ago
A Game Architecture for Emergent Story-Puzzles in a Persistent World
This paper presents the design of an architecture for narrative games with story-puzzles like classic graphic adventures. The system is able to create new short stories in each se...
Federico Peinado, Pedro Pablo Gómez-Mart&ia...
178
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CCGRID
2010
IEEE
15 years 7 months ago
A High-Level Interpreted MPI Library for Parallel Computing in Volunteer Environments
Idle desktops have been successfully used to run sequential and master-slave task parallel codes on a large scale in the context of volunteer computing. However, execution of messa...
Troy P. LeBlanc, Jaspal Subhlok, Edgar Gabriel
FPL
2010
Springer
188views Hardware» more  FPL 2010»
15 years 4 months ago
SeqHive: A Reconfigurable Computer Cluster for Genome Re-sequencing
We demonstrate how Field Programmable Gate Arrays (FPGAs) may be used to address the computing challenges associated with assembling genome sequences from recent ultra-high-through...
Kristian Stevens, Henry Chen, Terry Filiba, Peter ...