194 search results - page 13 / 39 » A static power model for architects |
214
click to vote
VLSID
2002
IEEE
16 years 6 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
154
click to vote
DAC
2005
ACM
15 years 8 months ago
2005
ACM
This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate ...
143
click to vote
ICCAD
2001
IEEE
16 years 2 months ago
2001
IEEE
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
177
click to vote
OOPSLA
2010
Springer
15 years 4 months ago
2010
Springer
As software becomes increasingly complex and difficult to analyze, it is more and more common for developers to use high-level, type-safe, object-oriented (OO) programming langua...
166
click to vote
ISCAS
2008
IEEE
16 years 13 days ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...