4400 search results - page 860 / 880 » A proposal for parallel self-adjusting computation |
144
click to vote
HPCA
2006
IEEE
16 years 6 months ago
2006
IEEE
Measurements of an off-the-shelf DRAM chip confirm that different cells retain information for different amounts of time. This result extends to DRAM rows, or pages (retention tim...
154
click to vote
HPCA
2006
IEEE
16 years 6 months ago
2006
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
153
click to vote
HPCA
2006
IEEE
16 years 6 months ago
2006
IEEE
As increasingly larger memories are used to bridge the widening gap between processor and disk speeds, main memory energy consumption is becoming increasingly dominant. Even thoug...
156
click to vote
HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...
168
click to vote
HPCA
2005
IEEE
16 years 6 months ago
2005
IEEE
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...