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» A proposal for parallel self-adjusting computation
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IPPS
2009
IEEE
16 years 1 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
PDCAT
2009
Springer
16 years 1 months ago
A Speculative Technique for Auto-Memoization Processor with Multithreading
—We have proposed an auto-memoization processor. This processor automatically and dynamically memoizes both functions and loop iterations, and skips their execution by reusing th...
Yushi Kamiya, Tomoaki Tsumura, Hiroshi Matsuo, Yas...
ICPP
2008
IEEE
16 years 1 months ago
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a f...
Sangyeun Cho, Socrates Demetriades, Shayne Evans, ...
IPPS
2008
IEEE
16 years 1 months ago
Intermediate checkpointing with conflicting access prediction in transactional memory systems
Transactional memory systems promise to reduce the burden of exposing thread-level parallelism in programs by relieving programmers from analyzing complex inter-thread dependences...
M. M. Waliullah, Per Stenström
IPPS
2008
IEEE
16 years 1 months ago
DC-SIMD : Dynamic communication for SIMD processors
SIMD (single instruction multiple data)-type processors have been found very efficient in image processing applications, because their repetitive structure is able to exploit the...
Raymond Frijns, Hamed Fatemi, Bart Mesman, Henk Co...