Sciweavers

4400 search results - page 162 / 880
» A proposal for parallel self-adjusting computation
Sort
View
JAL
2008
89views more  JAL 2008»
15 years 6 months ago
Experimenting with parallelism for the instantiation of ASP programs
Abstract. In the last few years, the microprocessors technologies have been definitely moving to multi-core architectures, in order to improve performances as well as reduce power ...
Francesco Calimeri, Simona Perri, Francesco Ricca
CODES
2005
IEEE
16 years 4 days ago
Improving superword level parallelism support in modern compilers
Multimedia vector instruction sets are becoming ubiquitous in most of the embedded systems used for multimedia, networking and communications. However, current compiler technology...
Christian Tenllado, Luis Piñuel, Manuel Pri...
BMCBI
2010
132views more  BMCBI 2010»
15 years 6 months ago
Parallel multiplicity and error discovery rate (EDR) in microarray experiments
Background: In microarray gene expression profiling experiments, differentially expressed genes (DEGs) are detected from among tens of thousands of genes on an array using statist...
Wayne Wenzhong Xu, Clay J. Carter
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
16 years 2 days ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
SBACPAD
2007
IEEE
129views Hardware» more  SBACPAD 2007»
16 years 23 days ago
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications
The necessity of devising novel thread-level speculation (TLS) techniques has become extremely important with the growing acceptance of multi-core architectures by the industry. H...
Md. Mafijul Islam