Functional validation of a processor design through execution of a suite of test programs is common industrial practice. In this paper, we develop a high-level architectural speci...
Thanh Nga Dang, Abhik Roychoudhury, Tulika Mitra, ...
In this paper, a novel automatic approach for the concurrent topology and routing optimization that achieves a high quality network layout is proposed. This optimization is based ...
Adaptation in embedded processing is key in order to address efficiency. The concept of extensible embedded processors works well if a few a-priori known hot spots exist. However,...
This paper presents a power grid analyzer based on a random walk technique. A linear-time algorithm is first demonstrated for DC analysis, and is then extended to perform transien...
Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar
The advent of strong multi-level partitioners has made topdown min-cut placers a favored choice for modern placer implementations. We examine terminal propagation, an important st...