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TCAD
2008
103views more  TCAD 2008»
15 years 6 months ago
Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
Latency-insensitive protocols allow system-on-chip (SoC) engineers to decouple the design of the computing cores from the design of the intercore communication channels while follo...
Rebecca L. Collins, Luca P. Carloni
DAC
2001
ACM
16 years 7 months ago
Speculation Techniques for High Level Synthesis of Control Intensive Designs
The quality of synthesis results for most high level synthesis approaches is strongly a ected by the choice of control ow through conditions and loops in the input description. In...
Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dut...
ICCD
2008
IEEE
124views Hardware» more  ICCD 2008»
16 years 3 months ago
Global bus route optimization with application to microarchitectural design exploration
— Circuit and processor designs will continue to increase in complexity for the foreseeable future. With these increasing sizes comes the use of wide buses to move large amounts ...
Dae Hyun Kim, Sung Kyu Lim
NOMS
2008
IEEE
134views Communications» more  NOMS 2008»
16 years 1 months ago
Manageability design for an autonomic management of semi-dynamic web service compositions
Abstract—Web service compositions (WSC), as part of a serviceoriented architecture (SOA), have to be managed to ensure compliance with guaranteed service levels. In this context,...
Christof Momm, I. P. Hallerbach, Sebastian Abeck, ...
NOCS
2007
IEEE
16 years 1 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni