Sciweavers

6129 search results - page 396 / 1226
» A parallel LLL algorithm
Sort
View
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
16 years 3 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
LCPC
2004
Springer
16 years 6 days ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
FOCS
2000
IEEE
15 years 11 months ago
Fast parallel circuits for the quantum Fourier transform
We give new bounds on the circuit complexity of the quantum Fourier transform (QFT). We give an upper bound of Ç´ÐÓ Ò · ÐÓ ÐÓ ´½ µµ on the circuit depth for computin...
Richard Cleve, John Watrous
COR
2006
96views more  COR 2006»
15 years 6 months ago
Scheduling two parallel machines with a single server: the general case
This paper considers the problem of scheduling two-operation non-preemptable jobs on two identical semiautomatic machines. A single server is available to carry out the first (or ...
Amir H. Abdekhodaee, Andrew Wirth, Heng-Soon Gan
IPPS
2009
IEEE
16 years 1 months ago
Deadlock prevention by turn prohibition in interconnection networks
Abstract—In this paper we consider the problem of constructing minimal cycle-breaking sets of turns for graphs that model communication networks, as a method to prevent deadlocks...
Lev B. Levitin, Mark G. Karpovsky, Mehmet Mustafa