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SASP
2009
IEEE
170views Hardware» more  SASP 2009»
16 years 1 months ago
Parade: A versatile parallel architecture for accelerating pulse train clustering
— In this paper, we present Parade, a novel and flexible parallel architecture for the deinterleaving of combined pulsetrains. This is a commonly performed task in various areas ...
Amin Ansari, Dan Zhang, Scott A. Mahlke
EUROPAR
2009
Springer
16 years 1 months ago
PSPIKE: A Parallel Hybrid Sparse Linear System Solver
The availability of large-scale computing platforms comprised of tens of thousands of multicore processors motivates the need for the next generation of highly scalable sparse line...
Murat Manguoglu, Ahmed H. Sameh, Olaf Schenk
IPPS
2006
IEEE
16 years 25 days ago
Oblivious parallel probabilistic channel utilization without control channels
The research interest in sensor nets is still growing because they simplify data acquisition in many applications. If hardware resources are very sparse, routing algorithms cannot...
Christian Schindelhauer
FPGA
2003
ACM
154views FPGA» more  FPGA 2003»
16 years 16 hour ago
Parallel placement for field-programmable gate arrays
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
Pak K. Chan, Martine D. F. Schlag
IPPS
2002
IEEE
15 years 11 months ago
A Parallel Ultra-High Resolution MPEG-2 Video Decoder for PC Cluster Based Tiled Display Systems
This paper presents a hierarchical parallel MPEG-2 decoder for playing ultra-high-resolution videos on PC cluster based tiled display systems. To maximize parallelism while minimi...
Han Chen, Kai Li, Bin Wei