405 search results - page 47 / 81 » A novel cache architecture with enhanced performance and sec... |
153
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ASPLOS
2010
ACM
15 years 9 months ago
2010
ACM
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...
174
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REFLECTION
2001
Springer
15 years 10 months ago
2001
Springer
, are to address what we perceive as the most pressing shortcomings of current reflective middleware platforms. First, performance: in the worst case, this needs to be on a par wit...
157
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ASPLOS
2010
ACM
16 years 29 days ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
171
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ARITH
2001
IEEE
15 years 9 months ago
2001
IEEE
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
139
Voted
GLOBECOM
2006
IEEE
16 years 4 days ago
2006
IEEE
— Multimedia applications communicating over a next generation VPN architecture that allows selective encryption can leverage the security properties of a VPN with its performanc...