405 search results - page 16 / 81 » A novel cache architecture with enhanced performance and sec... |
136
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ASPLOS
2006
ACM
16 years 1 days ago
2006
ACM
Cycles per Instruction (CPI) stacks break down processor execution time into a baseline CPI plus a number of miss event CPI components. CPI breakdowns can be very helpful in gaini...
177
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INFOSCALE
2007
ACM
15 years 7 months ago
2007
ACM
— To address the rapid growth of the Internet, modern Web search engines have to adopt distributed organizations, where the collection of indexed documents is partitioned among s...
199
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IEEEPACT
2007
IEEE
16 years 11 days ago
2007
IEEE
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
166
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ISCA
2006
IEEE
16 years 2 days ago
2006
IEEE
Protection from hardware attacks such as snoopers and mod chips has been receiving increasing attention in computer architecture. This paper presents a new combined memory encrypt...
124
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DATE
2009
IEEE
16 years 24 days ago
2009
IEEE
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...